1. Field of the Invention
The invention relates to a method for forming p-type doped gate electrodes during manufacture of CMOS semiconductor structures without boron penetration into the channel region and without boron depletion near the gate oxide.
2. Description of The Related Art
It is known that, in forming a gate on a substrate during manufacturing of a semiconductor device, large grain poly-silicon is used as the gate material. However, due to the fact that the surface of the layer formed by the large grain poly-silicon is rough because of the size of the grain, UV exposure light is scattered upon patterning the poly-silicon layer to form gates. Unfortunately, when this happens, the critical dimension of the gate is extremely difficult to control and uniformity of the gate cannot be obtained.
To resolve this problem in the conventional method of manufacturing semiconductor devices, amorphous silicon (a-Si) is employed as the gate material on a substrate. Because the surface of the layer formed by an a-Si is far smoother than that of large-grain poly-silicon, satisfactory critical dimension and uniformity of the gate maybe obtained. Nevertheless, in later thermal processes, the a-Si re-crystallizes at elevated temperatures to form large-grain poly-silicon. The formation of large-grain poly-silicon produces a channeling effect at the interface between the poly-silicon gate and the gate oxide layer. This channeling effect causes penetration of conductive ions i.e. p-type ion dopants, such as the boron ion, through the large-grain poly-silicon into the gate oxide.
U.S. Pat. No. 6,221,744 B1 disclose a method for forming a gate on a substrate during manufacturing of a semiconductor device. The process comprises:
forming a gate oxide layer on the substrate;
forming a polysilicon layer on the gate oxide layer;
forming an amorphous silicon layer on the polysilicon layer, wherein the amorphous silicon layer includes grains defining a plurality of first sizes;
defining the amorphous silicon layer and the polysilicon layer to form a gate structure; and
converting a first part of the grains of the amorphous silicon layer to polysilicon grains defining a plurality of second sizes so as to form a grain boundary between the amorphous silicon layer and the polysilicon layer, wherein each second size is smaller than the first size of the amorphous silicon layer grain.
Gate and field effect transistors including amorphous impurity layers are disclosed in U.S. Pat. No. 6,159,810. These gate electrodes for integrated circuit field effect transistors are fabricated by forming a polysilicon layer on a gate insulating layer, forming an amorphous impurity layer on the polysilicon layer, and forming an amorphous silicon layer on the amorphous impurity layer.
More specifically, a polysilicon layer 15 is formed on the gate insulating layer 13. The polysilicon layer may be doped with an n-type impurity, such as arsenic or phosphorus, or a p-type impurity such as boron. In FIG. 4, an amorphous impurity layer 17 is formed on the polysilicon layer 15 . . . The amorphous impurity layer 17 may be formed using plasma processing, ion implantation and/or other techniques. Then, as shown in FIG. 5, an amorphous silicon layer 19 is formed on the amorphous impurity layer 17 . . . Then, referring back to FIG. 2, the amorphous impurity layer 17 and the amorphous silicon layer 19 are converted into a polysilicon gate electrode having a first surface 201a adjacent the gate insulating layer 113, a second surface 201b opposite the gate insulating layer and a buried doped layer within the polysilicon gate electrode that is spaced apart from the first and second surfaces thereof. During this conversion, dopants in the amorphous impurity layer 117 may diffuse upward and downward into the polysilicon gate electrode 201, to form a doping profile that peaks within the polysilicon gate electrode 201.″ (col. 5, line 24-col. 6, line 4).
U.S. Pat. No. 5,278,096 disclose a gate formation method with an undoped poly-silicon layer.
Formed upon polysilicon layer 15 is tungsten silicide layer 17 . . . Layer 17 is desirably formed by sputtering . . . The sputtering process produces a comparatively amorphous layer (col. 2, lines 18-27). Layer 19 is formed upon layer 17. Layer 19 may be any dielectric formed at a sufficiently low temperature to prevent crystallization of silicide layer 17 . . . Reference numeral 23 denotes an implantation species which may be, typically, elemental boron . . . [T]he peak of the implantation dosage is near the top surface of silicide layer 17 in the as-implanted stage. Little boron penetrates into polysilicon layer 15. After the implantation is performed, an annealing step, typically 30 minutes at approximately 900° C., is performed. The annealing step drives boron dopant from silicide 17 into polysilicon layer 15.″ (col. 2, line 33-col. 3, line 2).
A method of manufacturing a CMOS semiconductor device is disclosed in U.S. Pat. No. 5,464,789. The method includes: forming a polysilicon film over a gate oxide film, forming a film of an amorphous material over the polysilicon film, and implanting boron atoms into the polysilicon film through the film of amorphous material.
In the aggressive scaling of CMOS devices to smaller feature sizes wherein there is the requirement of the use of surface-channel pMOSFET to minimize the short-channel effect to improve device performance, wherein a p-type doped gate electrodes must inevitably be used to realize the surface-channel pMOSFET, and wherein formation of p-type doped gate electrodes is very difficult due to severe boron penetration into the channel region during subsequent high-thermal processes, and wherein to suppress boron penetration low thermal processing is required but leads to boron depletion near the gate oxide, there is a need to devise a process wherein a p-type doped gate electrode may be formed without boron penetration into the channel region and without boron depletion near the gate oxide.